1. Field of the Invention
The present invention relates to flash semiconductor memory, and more particularly to serial flash semiconductor memory.
2. Description of the Related Art
Electronic systems have traditionally used parallel “NOR” flash memories for non-volatile code storage, and in some cases data storage. Newer serial flash memories, with their low pin-count and small packaging, are an alternative to ordinary parallel flash memories for code and data storage requirements. As a result, the use of serial flash memory is gaining momentum. Diverse applications such as graphics cards, hard drives, printers, wireless networking, set-top boxes, DVD drives and players, DSL modems, field programmable gate arrays, and other applications are turning to serial flash memory to reduce controller pin count, board space, power consumption, noise, and overall system costs.
A significant difference between serial flash memory and parallel flash memory has to do with interface pins and packaging. Serial flash memory typically have data, control and power pins, but no dedicated address pins. Most serial flash memories use the popular four-pin Serial Peripheral Interface (“SPI”) protocol, and are typically housed in low pin count packages such as the 8-pin or 16-pin Small Outline Integrated Circuit (“SOIC”) package and the 8-contact Micro Leadframe Package (“MLP”) (also referred to as Quad Flat No-lead (“QFN”) and Small Outline No-lead (“SON”). An 8-pin SOIC or MLP package uses less than 25 percent the space of a parallel flash package. In contrast, parallel flash memories typically require 22 to 44 address, data and control pins, and are commonly packaged in 32-pin Plastic Leaded Chip Carrier (“PLCC”) and 40 to 56-pin Thin Small Outline Package (“TSOP”) packages. Relative space requirements are evident from FIG. 1, which shows a parallel flash package 12 adjacent a serial flash package 14. A standard paperclip 10 is shown for scale. Relative pin-out and space requirements are evident from FIG. 2, which shows a pinout diagram for parallel flash package 20 and serial flash package 22. Serial Flash densities typically range from 512 K-bit to 128 M-bit, although advanced 0.18 micron technologies can fit higher densities of 4 M-bit and greater into small 8-pin packaging. Examples of typical serial flash memories are disclosed in the data sheets for part numbers NX25P10/20/40 and NX25P80/16/32, which are available from NexFlash Technologies Inc. of San Jose, Calif.
The SPI protocol specifies a four wire interface, namely clock (CLK), chip select (/CS), data in (DI) and data out (DO). Power is provided through the VCC and GND pins. Optional write-protect /WP and hold /HOLD pins are commonly provided. The write-protect pin is used for additional hardware protection of the memory. The hold pin allows the device to be suspended during an instruction, which can be useful if multiple devices are sharing the same SPI bus. These pins can simply be tied high if not used. These pins are shown in FIG. 2.
A variety of other serial specifications have been proposed, including MICROWIRE, I2C (Inter IC bus), and NXS. The MICROWIRE specification is a two data pin DI and DO interface similar to the SPI specification. The I2C and NXS protocols specify a bit serial data IO pin. The SPI and NXS protocols are described in the following patents, which are hereby incorporated herein by reference in their entirety: U.S. Pat. No. 6,175,517, issued Jan. 16, 2001 to Jigour et al. and entitled “Insertable and removable digital memory apparatus,” U.S. Pat. No. 6,026,007, issued Feb. 15, 2000 to Jigour et al. and entitled “Insertable and removable high capacity digital memory apparatus and methods of operation thereof,” U.S. Pat. No. 5,877,975, issued Mar. 2, 1999 to Jigour et al. and entitled “Insertable/removable digital memory apparatus and methods of operation thereof,” U.S. Pat. No. 5,815,426, issued Sep. 29, 1998 to Jigour et al. and entitled “Adapter for interfacing an insertable/removable digital memory apparatus to a host data port,” and U.S. Pat. No. 5,291,584, issued Mar. 1, 1994 to Challa et al. and entitled “Method and Apparatus for Hard Disk Emulation.” While the use of eight contact pads is common for these protocols, fewer contact pads would be entirely satisfactory for some applications and the interface protocols would be adjusted accordingly.
FIG. 3 is a set of graphs showing a clocking diagram of a read instruction that is common among serial flash memories. After chip select is asserted low as shown at 30, a single read instruction byte (03hex) is clocked into the device as shown at 32, followed by a 24-bit address as shown at 34. Data may be continuously clocked out of the serial flash memory from the starting address as shown at 36, until chip select is raised (not shown).
Due to historical reasons, the architectures of standard processors or microcontrollers boot and execute code from a parallel interface. However, many system-on-a-chip ASIC controllers are moving away from the old parallel flash interface and are now using serial flash for code storage. Serial code storage, also referred to as code shadowing, is a design technique that initially appeared with complex graphics and hard drive controllers, and has now expanded to a broad range of high performance applications. These controller-based systems were often downloading code upon power-up from parallel flash memory to faster RAM, a function that Serial Flash can handle more efficiently and cost effectively, as will be appreciated from a comparison of FIG. 4 and FIG. 5.
FIG. 4 shows an application specific controller 48 with a high-speed RAM (RAM, DRAM or SDRAM) interface 49 and a parallel flash memory 40. Due to interface compatibility and performance issues, the parallel flash memory is often separate from the RAM interface, and requires 17 to 22 address lines 44, an 8-bit or 16-bit data bus 46, and three to six control lines 42. This is a considerable overhead for most application specific controllers.
FIG. 5 shows an application specific controller 54 using a serial flash memory with a four-pin SPI interface 52 for serial code storage. In this arrangement, the controller 54 upon power-up boots either from internal ROM (not shown) or from code that has been transferred from the serial flash 50 to either internal RAM 56 or external RAM 58 using a single read command. Typically all or a significant part of the code in the flash memory 50 is transferred to the RAM 56 or RAM 58 and is executed from the RAM 56 or RAM 58, as appropriate. Code segments can also be transferred dynamically to the RAM 56 or RAM 58 as needed after power-up.
Systems that use serial flash memory realize significant benefits. Removing the parallel flash interface frees controller pins for other purposes, or may enable the controller to fit into a smaller and lower-cost package. The tiny and low-pin-count serial flash packaging allows the printed circuit board to be smaller with fewer traces, further reducing costs. Transient switching noise, common with parallel address and data busses, is eliminated. Additionally, serial flash tends to consume less power during read than parallel flash. Moreover, once the code is downloaded, serial flash can be placed into low power (microamp) stand-by to further minimize supply requirements. In those cases where parallel flash was originally used for code execution, switching to serial code storage with execution out of RAM also increases performance. Additionally, code can be compressed in the serial flash and decompressed when downloaded for greater storage capacity.
Besides the user benefits of serial flash, there are manufacturer benefits as well. Serial flash packages are smaller and use fewer pins so they cost less than parallel flash packages, especially for popular 8-pin SOIC packages. With fewer pins, there are fewer I/O pads on the die, resulting in smaller die sizes and lower die costs. Additionally, fewer pins mean many more devices can be tested simultaneously. Since flash memory test costs represent a significant portion of the overall product cost, serial flash provides a more cost effective solution.
Despite significant advantages of serial flash over parallel flash, parallel flash memories retain some advantages over serial flash memories. One of these is faster transfer speed. Since a system cannot operate until its code is downloaded, fast serial flash clock speed is desirable. Most serial flash memories today support clock frequencies in the range of 20 MHz, and some devices support SPI read clock speeds from 33 MHz to 50 MHz. At these clock rates, it can take from 20 milliseconds to 52 milliseconds to transfer 1 M-bit of code. While this may be acceptable for lower density serial flash of less than 4 M-bit, for example, the power-up delay can increase as density requirements increase. For example, transferring 64 M-bits of code at 50 MHz takes over 1.3 seconds. In contrast, a parallel flash memory with a 16-bit data bus and 70 nS access time can transfer the same amount of code three to four times faster.
For systems that do not operate from internal or external RAM, another advantage of parallel flash memory over serial flash memory is code execution. The architecture of many parallel flash memories provides 3-6 control pins, 17-22 address pins, and an 8 or 16-bit data pins that interface with standard processors or microcontrollers. Micro-code can be executed directly from the parallel flash memory using small amounts of locally dedicated memory or registers, with random memory access for jumps and calls, as well as fast data transfers using direct memory access (DMA) techniques being supported.
Code execution on a serial flash memory is not practical because of the amount of overhead required. Basically in a serial flash memory system, the controller would serially shift each read instruction with a memory address one bit at a time, requiring typically, for example, 32 clocks. A memory read of parallel flash, in contrast, can be made in one or a few clocks because the address and data are transferred in parallel. The overhead of a serial flash is further increased when the instruction sequence encounters frequent address jumps or calls, each of which would require another serial read instruction to be shifted in bit-by-bit. Even at the fastest serial flash clock rates, such a system would be significantly slower than a parallel flash memory.
Some flash memories have attempted to incorporate both serial and parallel buses in their design. The type AT45DB642 flash memory available from Atmel Corporation of San Jose, Calif., for example, has added an 8-bit parallel data bus as a user-selectable alternative to the standard SPI bus; see Atmel Corporation, AT45DB642 Data Sheet, 2002. However, the clock frequency is reduced by 75% when using the parallel interface, substantially limiting the net gain in transfer rate. Additionally the device has 20 signal and power pins and in housed in a 40-pin TSOP, which is contrary to the most fundamental Serial Flash advantages of lower pin count and smaller packaging.
Since existing flash memory systems of the serial and parallel type have significant disadvantages, there is need for a device that can support existing interfaces yet allow for increased performance and features as needed in the application.